Deterministic distributed multi-cache coherence method and system
US5893160A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1996 |
| Grant date | Apr 6, 1999 |
| Priority date | — |
| Expiry date | Apr 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An efficient streamlined coherent protocol for a multi-processor multi-cache computing system. Each subsystem includes at least one processor and an associated cache and directory. The subsystems are coupled to a global interconnect via global interfaces. In one embodiment, each global interface includes a request agent (RA), a directory agent (DA) and a slave agent (SA). The RA provides a subsystem with a mechanism for sending read and write request to the DA of another subsystem. The DA is responsible for accessing and updating its home directory. The SA is responsible for responding to requests from the DA of another subsystem. Each subsystem also includes a blocker coupled to a DA and associated with a home directory. All requests for a cache line are screened by the blocker associated with each home directory. Blockers are responsible for blocking new request(s) for a cache line until an outstanding request for that cache line has been serviced. A "locked" state managed by the blocker greatly reduces corner cases and simplifies solutions in the few remaining corner cases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.