Method for simultaneously forming local interconnect with silicided elevated source/drain MOSFET's
US5893741A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 1997 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Feb 7, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0275
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for formation of both local innerconnection and silicidation of source/drain transistors using the deposition of a blanket silicon layer over the entire top surface of the transistors and selectively stripping of unwanted portions of the silicon layer is disclosed. The method includes the step of applying a photoresist mask to map out where the local interconnection and source/drain are to be located. The final recited step is to deposit a thin metal layer to provide for the silicidation to complete the transistor. The silicon layer that is deposited has a thickness of 20 to 300 millimeters, and the thin metal layer is either cobalt or titanium having a thickness of 10 millimeters to 100 millimeters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.