Cell density improvement in planar DMOS with farther-spaced body regions and novel gates
US5894150A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 8, 1997 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Dec 8, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/151
Abstract
This invention discloses a DMOS planar power device having a plurality of transistor cells formed in a semiconductor substrate with a drain region of a first conductivity type disposed at a bottom surface of the substrate. Each of the DMOS transistor cells includes a polysilicon segment constituting a gate supported on a top surface of the substrate wherein the gate being disposed substantially in a center portion of the transistor cell. The DMOS transistor cell further includes a source region of the first conductivity type disposed in the substrate surrounding edges of the gate with a portion extends underneath the gate. The DMOS transistor cell further includes a body region doped with a body dopant of a second conductivity type disposed in the substrate encompassing the source region. The body region has a portion extending underneath the gate having a under-the-gate distance less than a lateral diffusion of the body dopant and the body region having outer edges extending outwardly to neighboring transistor cells. The DMOS transistor cell further includes a shallow low-concentration first-conductivity-type region under the gate wherein the shallow low-concentration first-conduc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.