Flexible reset scheme supporting normal system operation, test and emulation modes
US5894176A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 1994 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | May 4, 2014 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A structure and a method are provided to implement a reset scheme for an integrated circuit supporting a variety of testing and debugging equipment. The control and I/O pins of the integrated circuit are each set to a high impedance state when the signals of a reset pin and a mode pin are both asserted. If the signal on the mode pin remains asserted at the time the signal on the reset pin is negated, the control and I/O pins of the integrated circuit remain in the high impedance state until the next time the signal on the reset pin is asserted. Otherwise, the control and I/O pins of the integrated circuits are enabled upon negation of the signal on the reset pin. In one embodiment, the mode pin is multiplexed with an pin used for receiving interrupt signals during functional operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.