Mechanism for enabling multi-bit counter values to reliably cross between clocking domains
US5894567A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1995 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Sep 29, 2015 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A queue structure for transmitting a multiple-bit signal from a first sub-system operating in a first clocking domain in a computer system to a second sub-system operating in a second clocking domain in the computer system is disclosed. The queue structure comprises a queue data latch having a plurality of storage elements, wherein each of the plurality of storage elements can store the multiple-bit signal from the first sub-system. A load pointer is used for generating a first multiple-bit count indicating one of the plurality of storage element for storing the multiple-bit signal. A synchronization unit is coupled to the load pointer for receiving the first multiple-bit count. The synchronization unit outputs the multiple-bit count at the second sub-system when the multiple-bit signal is ready to be sampled in the second clocking domain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.