Method and system for initial state determination for instruction trace reconstruction
US5894575A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 25, 1996 |
| Grant date | Apr 13, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for determining an initial architectural state for instruction trace reconstruction. Performance projections for processor systems and memory subsystems are important for a correct understanding of work loads within the system. An instruction trace is generally utilized to determine distribution of instructions, identification of register dependencies, branch path analyses and timing. One well-known technique for reconstructing an instruction trace can be accomplished by monitoring bus traffic to determine instruction addresses, data addresses and data during the trace. However, the initial architectural state (the state of all caches, buffers and registers) must be determined in order to accurately reconstruct an instruction trace. At least one cache within the processor system is divided into two portions, the content of that cache is invalidated and each cache entry thereafter is duplicated within each portion of the divided cache. Upon initiation of an instruction trace, one half of the cache is frozen, preserving the initial state of the system with respect to that cache without requiring the cache to be invalidated and refilled during the instruction trace…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.