Tapered dielectric etch in semiconductor devices
US5895937A · kind A · utility
41Cited by
8References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 21, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Oct 21, 2017 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/978
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.