Silicon carbide field effect transistor with increased avalanche withstand capability
US5895939A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 9, 1998 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Apr 9, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8325
Abstract
A vertical SiC trench MOSFET power switching FET includes a gate electrode in the trench. The MOSFET adds a buried region of a first conductivity type, more heavily doped than a base layer of the first conductivity type, to the base layer except adjacent to the trench. The buried region is preferably disposed in the base layer, or between a drift layer of a second conductivity type and the base layer. The region of the first conductivity type is optionally disposed below the bottom of the trench to encourage expansion of the depletion layer of the MOSFET. A depletion-type vertical SiC MESFET of the invention includes a buried region of the first conductivity type in a base layer of a second conductivity type. A Schottky electrode on a portion of the base layer above the buried region ensures adequate expansion of a depletion layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.