Intergrated circuit memory devices including capacitors on capping layer
US5895947A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 16, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Jun 16, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/315
Abstract
Integrated circuit memory devices are fabricated by forming a first contact hole in a cell array region and a second contact hole in a peripheral circuit region. Conductive material is simultaneously placed in the first and second contact holes such that the conductive material in the first contact hole electrically contacts a memory cell transistor in the cell array region and the conductive material in the second contact hole electrically contacts the peripheral circuit transistor in the peripheral circuit region. A capping layer is included, and the peripheral circuit region wiring layer and the capacitor storage electrode is formed directly on the capping layer. Improved performance and reduced step height may thereby be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.