Ki-Nam Kim
160Patents
19h-index
207Co-inventors
89Inventor score
Filing activity: Sep 25, 1989 → Jul 6, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6297090A | Method for fabricating a high-density semiconductor memory device | Emerging Cross-Sectional Technologies | 149 | Expired |
| US6388281B1 | Triple metal line 1T/1C ferroelectric memory device and method for fabrication thereof | Electricity | 55 | Expired |
| US7542350B2 | Methods of restoring data in flash memory devices and related flash memory device memory systems | Physics | 48 | Active |
| US6613621B2 | Methods of forming self-aligned contact pads using a damascene gate process | Electricity | 42 | Expired |
| US6133116A | Methods of forming trench isolation regions having conductive shields therein | Electricity | 40 | Expired |
| US6961271B2 | Memory device in which memory cells having complementary data are arranged | Physics | 40 | Expired |
| US7675783B2 | Nonvolatile memory device and driving method thereof | Physics | 40 | Active |
| US7042760B2 | Phase-change memory and method having restore function | Physics | 39 | Expired |
| US5895947A | Intergrated circuit memory devices including capacitors on capping layer | Electricity | 27 | Expired |
| US7692970B2 | Flash memory devices that utilize age-based verify voltages to increase data reliability and methods of operating same | Physics | 26 | Active |
| US6350649B1 | Bit line landing pad and borderless contact on bit line stud with etch stop layer and manufacturing method thereof | Electricity | 26 | Expired |
| US7701771B2 | Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same | Electricity | 25 | Active |
| US6764941B2 | Bit line landing pad and borderless contact on bit line stud with localized etch stop layer and manufacturing method thereof | Electricity | 24 | Expired |
| US6787906B1 | Bit line pad and borderless contact on bit line stud with localized etch stop layer formed in an undermined region | Electricity | 23 | Expired |
| US6404001B2 | Multilevel conductive interconnections including capacitor electrodes for integrated circuit devices | Electricity | 22 | Expired |
| US6737694B2 | Ferroelectric memory device and method of forming the same | Electricity | 21 | Expired |
| US7560760B2 | Ferroelectric memory devices having expanded plate lines | Electricity | 20 | Active |
| US6262446A | Methods of forming multilevel conductive interconnections including capacitor electrodes for integrated circuit devices | Electricity | 20 | Expired |
| US6198651A | Ferroelectric memory devices which utilize boosted plate line voltages to improve reading reliability and methods of operating same | Physics | 19 | Expired |
| US7508732B2 | Multi-bit flash memory device including memory cells storing different numbers of bits | Physics | 19 | Active |
| US6515323B1 | Ferroelectric memory device having improved ferroelectric characteristics | Electricity | 18 | Expired |
| US8791405B2 | Optical waveguide and coupler apparatus and method of manufacturing the same | Physics | 17 | Active |
| US9720449B2 | Flexible display device including touch sensor | Emerging Cross-Sectional Technologies | 17 | Active |
| US6391736B1 | Method for fabricating a capacitor of a semiconductor device and a capacitor made thereby | Electricity | 16 | Expired |
| US9607419B2 | Method of fitting virtual item using human body model and system for providing fitting service of virtual item | Physics | 16 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.