Vertical bipolar SRAM cell, array and system, and a method of making the cell and the array
US5896313A · kind A · utility
22Cited by
7References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 2, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Jun 2, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM memory cell is provided in which a pair of cross-coupled n-type MOS pull-down transistors are coupled to respective parasitically formed bipolar pull-up transistors. The memory cell is formed within a semiconductor layer which extends over a buried layer. The bipolar transistors are formed parasitically from the buried layer and the semiconductor layer used to form the pull-down transistors. The bases of the bipolar transistors may also be dynamically controlled. An SRAM memory array having a plurality of such memory cells and a computer system incorporating the SRAM memory array are also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.