System and method for testing self-timed memory arrays
US5896399A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 1996 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Dec 11, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention applies a Static Evaluate technique to a memory array in a selective manner that allows some parts of the array to use the technique, and yet keeps the array area and timing unaffected for normal operation. The present invention allows the decode functions of the memory array to become pseudo-static during a first part of a clock cycle. In addition, if a write function is being performed, the write data is also held pseudo-static and is not written until a second part of a clock cycle when all addresses and data have stabilized. The invention can be used for system debug, product bring-up, or burn-in, even if there are non-functional race paths. A system and method of testing and burning in self-timed memory arrays includes a Static Evaluate circuit applied to the decoding function and the writing function of the array, a circuit for holding an address or write data inactive for the first part of a cycle, a circuit for activating the address or write data for the second part of a cycle, and a circuit for ensuring that the array resets correctly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.