Logic implementation of control signals for on-silicon multi-master data transfer bus
US5896514A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 23, 1997 |
| Grant date | Apr 20, 1999 |
| Priority date | — |
| Expiry date | Aug 23, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4072
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Within a single integrated circuit, a bus operates in accordance with a bus protocol. The bus protocol includes a first control signal which, when not implemented within a single integrated circuit, is implemented using a pull-up resistor and tri-state gates within functional blocks attached to the bus. A first functional block includes a first input line for receiving an input component of the first control signal, and includes first logic means for generating a first output component of the first control signal. A second functional block includes a second input line for receiving the input component of the first control signal, and includes second logic means for generating a second output component of the first control signal. A logic block includes first logic for generating the input component of the first control signal. The first logic utilizes the first output component and the second output component to generate the input component of the first control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.