Low mask count self-aligned silicided CMOS transistors with a high electrostatic discharge resistance
US5897348A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 13, 1998 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Mar 13, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/811
Abstract
A method to fabricate simultaneously a CMOS transistor and an ESD protective transistor in a silicon substrate is disclosed. The NMOS transistor and PMOS transistor in the portion of the CMOS transistor have both anti-punchthrough and salicide structures and individually with n-LDD and p-LDD structure, respectively. The structure of ESD protective devices is fabricated with self-aligned silicide but without LDD, thus the degradation of ESD protection can be solved. The problems of accumulative aberration in scaled devices can also be alleviated through using blanket ion implantation technology and salicide process to reduce the mask count as shown in the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.