Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion
US5897352A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 25, 1998 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Mar 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/033
Abstract
A method for creating a stacked capacitor structure, with increased surface area, needed for high density, DRAM designs, has been developed. A storage node electrode, featuring a top surface of HSG polysilicon lumps, is used for the surface area increase. A feature of this invention is the use of a thin, heavily doped, polysilicon layer, formed on the HSG polysilicon lumps, resulting in improved adhesion between HSG polysilicon lumps and the underlying polysilicon storage node shape. The thin, heavily doped, polysilicon layer also supplies dopant to underlying HSG polysilicon lumps, needed to reduce a capacitor depletion phenomena which can occur if undoped HSG polysilicon lumps are used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.