Dahcheng Lin
22Patents
11h-index
6Co-inventors
60Inventor score
Filing activity: Mar 25, 1998 → Jul 11, 2002
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6046083A | Growth enhancement of hemispherical grain silicon on a doped polysilicon storage node capacitor structure, for dynamic random access memory applications | Electricity | 58 | Expired |
| US6037238A | Process to reduce defect formation occurring during shallow trench isolation formation | Electricity | 49 | Expired |
| US5913119A | Method of selective growth of a hemispherical grain silicon layer on the outer sides of a crown shaped DRAM capacitor structure | Electricity | 35 | Expired |
| US6037219A | One step in situ doped amorphous silicon layers used for selective hemispherical grain silicon formation for crown shaped capacitor applications | Emerging Cross-Sectional Technologies | 34 | Expired |
| US5897352A | Method of manufacturing hemispherical grained polysilicon with improved adhesion and reduced capacitance depletion | Electricity | 31 | Expired |
| US6074931A | Process for recess-free planarization of shallow trench isolation | Electricity | 30 | Expired |
| US5930625A | Method for fabricating a stacked, or crown shaped, capacitor structure | Electricity | 29 | Expired |
| US5877052A | Resolution of hemispherical grained silicon peeling and row-disturb problems for dynamic random access memory, stacked capacitor structures | Electricity | 25 | Expired |
| US6372572B1 | Method of planarizing peripheral circuit region of a DRAM | Electricity | 14 | Expired |
| US6194265A | Process for integrating hemispherical grain silicon and a nitride-oxide capacitor dielectric layer for a dynamic random access memory capacitor structure | Electricity | 11 | Expired |
| US6004859A | Method for fabricating a stack capacitor | Emerging Cross-Sectional Technologies | 11 | Expired |
| US6127221A | In situ, one step, formation of selective hemispherical grain silicon layer, and a nitride-oxide dielectric capacitor layer, for a DRAM application | Electricity | 10 | Expired |
| US6165830A | Method to decrease capacitance depletion, for a DRAM capacitor, via selective deposition of a doped polysilicon layer on a selectively formed hemispherical grain silicon layer | Electricity | 10 | Expired |
| US6822283B2 | Low temperature MIM capacitor for mixed-signal/RF applications | Electricity | 9 | Expired |
| US6100136A | Method of fabricating capacitor capable of maintaining the height of the peripheral area of the capacitor | Electricity | 8 | Expired |
| US6225214A | Method for forming contact plug | Electricity | 8 | Expired |
| US6130146A | In-situ nitride and oxynitride deposition process in the same chamber | Emerging Cross-Sectional Technologies | 5 | Expired |
| US6240015A | Method for reading 2-bit ETOX cells using gate induced drain leakage current | Physics | 5 | Expired |
| US6197652A | Fabrication method of a twin-tub capacitor | Electricity | 2 | Expired |
| US6162732A | Method for reducing capacitance depletion during hemispherical grain polysilicon synthesis for DRAM | Emerging Cross-Sectional Technologies | 1 | Expired |
| US6294437A | Method of manufacturing crown-shaped DRAM capacitor | Electricity | 1 | Expired |
| US6291294A | Method for making a stack bottom storage node having reduced crystallization of amorphous polysilicon | Electricity | 0 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.