Method for forming interconnection of a semiconductor device
US5897369A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 16, 1996 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Sep 16, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76885
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming an interconnection of a semiconductor device, includes the steps of forming an insulating layer on a substrate on which a lower conductive layer is formed, selectively removing the insulating layer to form a first connecting hole and a second connecting hole for the pattern of an upper conductive layer, growing a first conductive material in the first connecting hole to form a buried plug and then depositing a second conductive material on the surface of the insulating layer to form a barrier layer, and depositing a third conductive material on the barrier layer to fill the second connecting hole and then patterning it to form an upper conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.