Integrated circuit floor plan optimization system
US5898597A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Feb 11, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.