Non-volatile semiconductor memory device
US5898614A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | May 21, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | May 21, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5634
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-volatile semiconductor memory device comprises a plurality of memory cells each including a semiconductor substrate of a first conductivity type having a main surface region, a control gate portion formed in said main surface region of the semiconductor substrate and consisting of an impurity diffusion region of a second conductivity type opposite to said first conductivity type, a reading transistor portion formed on the main surface region of the substrate and consisting of a MOS type transistor structure, and a floating gate portion formed over the control gate portion and the reading transistor portion. These memory cells differ from each other in an overlapping area ratio Ap/An, where An denotes an area of an over-lapping portion between the floating gate and the impurity diffusion region of the control gate portion, Ap represents an area of an overlapping portion between the floating gate and an active region of the reading transistor portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.