Input port switching protocol for a random access memory
US5898623A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Oct 9, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high speed/narrow I/O DRAM device comprises both a data input/output (I/O) port as well as a command port for receiving commands used to control the operations of the DRAM. The command port is defined as input only (i.e., for inputting command data). The present invention comprises multiplexing write data to be written and stored in the DRAM onto the command port with command data packets. The data I/O port can then become dedicated to streaming out seamless data since it no longer needs to flip between input and output data. Even greater bus efficiency can be realized if, during a command packet transfer, data writes to the DRAM are switched back to the data I/O port. With this input port switching protocol, greater bus efficiency and increased memory performance can be realized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.