I/O bus interface recovery counter dependent upon minimum bus clocks to prevent overrun and ratio of execution core clock frequency to system bus clock frequency
US5898815A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1996 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Feb 13, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4226
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A bus interface unit of a processor comprises an I/O recovery counter for preventing peripheral overrun due to successive I/O bus cycles. The I/O recovery counter counts the necessary I/O recovery period between I/O bus cycles necessary to prevent peripheral overrun. The I/O recovery counter comprises a clock input from the processor and a signal derived from the bus control signal READY. The I/O recovery counter begins to count at the receipt of the READY signal after the initiation of an I/O bus cycle. The bus interface unit waits until the I/O recovery counter completes its count of the I/O recovery period prior to initiating another I/O bus cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.