Load instruction steering in a dual data cache microarchitecture
US5898852A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 1997 |
| Grant date | Apr 27, 1999 |
| Priority date | — |
| Expiry date | Jun 26, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for executing an instruction is provided. The instruction loads data into one of a plurality of registers in a register file and is in a first group of instructions. A second group of instructions is executed sequentially after the first group of instructions. The first and second groups of instructions should each include at least one instruction. The apparatus includes a first memory, a second memory, a first functional unit coupled to the first memory, and a second functional unit coupled to the first memory and to the second memory. The first and second functional units are both capable of executing the instruction. Also included is an instruction issue unit coupled to the first and the second functional units. The instruction issue unit issues the instruction to a selected functional unit selected from one of the first and the second functional units. This selection is based on a load prediction bit associated with the instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.