Sub-micron MOSFET

US5899719A · kind A · utility

Assignee

• United Semiconductor Corp. · TW

Inventor

• Gary Hong · Baoshan, TW

Key dates

• Filing date: Jul 7, 1997
• Grant date: May 4, 1999
• Expiry date: Jul 7, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/371

Abstract

A narrow gate FET is formed on a substrate by providing a first layer of polysilicon on the active device regions of the substrate and doping the polysilicon by ion implantation. An etch/polish stop layer of silicon oxide and is deposited on the first layer of polysilicon. Openings are formed in the etch/polish stop layer and the first polysilicon layer to expose the surface of the substrate. An anneal is performed to diffuse N-type impurities from the first layer of polysilicon into the substrate. The heavily doped portions of LDD source/drain regions are formed partially within the substrate and partially within portions of the first layer of polysilicon left on the surface of the substrate. Next, a first implantation of N-type impurities is made across the opening in the first layer of polysilicon. A layer of silicon nitride is deposited over the first layer of polysilicon and within the openings in the first polysilicon layer. Etching is performed to provide nitride spacers on the sidewalls of the openings. A second implantation of P-type impurities is performed to counterdope the channel and to laterally define the lightly doped portions of the source/drain regions. A gate oxi…