Method for forming a tapered spacer
US5899747A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 27, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Jan 27, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/671
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a gate with a tapered spacer is disclosed. The method includes forming a polysilicon layer on a substrate, and then forming a first oxide layer on the polysilicon layer. A photoresist layer is formed on the first oxide layer, where the photoresist layer defines a gate region, and then portions of the oxide layer and the polysilicon layer are removed using the photoresist layer as a mask, thereby forming a gate. A second oxide layer is formed on the substrate and the first oxide layer. Afterwards, the second oxide layer is isotropically etched so that the slope of the second oxide layer near the upper corners of the gate is reduced. Finally, the second oxide layer is anisotropically etched back to form spacers on the sidewalls of the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.