System for using a cache memory with a write-back architecture
US5900016A · kind A · utility
17Cited by
9References
40Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 2, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Apr 2, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes a microprocessor, a cache memory, main memory and supporting logic. The supporting logic includes cache control logic that determines whether an access to memory results in a hit to the cache for dirty or clean data. When a write to the cache results in a hit to clean data, the bus cycle is enlarged in order to set a dirty bit associated with the write data. The bus cycle is enlarged by requesting the processor to refrain from commencing a new bus cycle or driving a new memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.