Organic controlled collapse chip connector (C4) ball grid array (BGA) chip carrier with dual thermal expansion rates
US5900675A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Apr 21, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip package with an integrated chip carrier having differing coefficients of thermal expansion (CTE) in the x-y plane. The chip carrier is comprised of two main regions. The first is a core region having a CTE approximately equal to that of the semiconductor chip CTE. This core region also has approximately the same dimensions in the x-y plane as the semiconductor chip. The chip is mounted just above this core region. The second region is a peripheral region which surrounds the core region in the x-y plane. This second region has a CTE approximately equal to that of the printed circuit board CTE. During thermal cycling, the materials expand and contract. The core region expands at nearly the same rate as the chip and the area outside the chip footprint, the peripheral region, expands at a rate similar to that of the printed circuit board. This characteristic prevents thermal stress-induced fatigue on the package components and solder joints.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.