Threshold voltage level generator for time division duplex communications
US5900749A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | May 14, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A circuit for generating a threshold voltage level from a time division duplex analog data signal. The circuit comprises a sample/hold circuit and an amplifier. The sample/hold circuit is arranged to sample the threshold voltage level during a reception interval and hold the threshold voltage level during a transmission interval. The amplifier includes an operational amplifier coupled to the sample/hold circuit for amplifying the analog data signal during a reception interval and amplifying the threshold voltage level during a transmission interval. A transconductance device is coupled to the operational amplifier, and a plurality of load legs are respectively coupled to a plurality of bias legs. A first selected pair of the respectively coupled load legs and bias legs is coupled to the transconductance device, and a second selected pair of the respectively coupled load legs and bias legs coupled to the output of the amplifier to provide the threshold voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.