Asynchronous interface
US5900753A · kind A · utility
50Cited by
7References
67Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 28, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Mar 28, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F5/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface allowing to transfer serial test data from a Test Access Port (TAP) to controllers located in several clock domains is described. The clock frequencies can be different from each other and do not need to be related in phase to each other or with the clock of the TAP. The interface is proven to work reliably as long as the clock frequencies used for the test controllers and registers is 3 times higher than the one of the TAP used to source the serial test data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.