Variable voltage isolation gate and method
US5901078A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 19, 1997 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Jun 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4091
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A variable voltage is provided to gates of isolation transistors in DRAM devices between digit lines containing many storage cells and a sense amplifier. The gate of the isolation transistor is provided a voltage pumped higher than the supply voltage during read time to ensure that a small differential voltage on the digit lines is correctly read. A lower voltage is provided at sense time such that the isolation gate provides a higher resistance during sense time. During restore time, the isolation gate voltage is again raised above the operating voltage to minimize the effects of isolation transistor threshold voltage, Vt. In further embodiments, the higher voltage is only provided during restore time and the read and sense voltages are varied between the higher and lower voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.