Endurance testing system for an EEPROM
US5901082A · kind A · utility
2Cited by
1References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1998 |
| Grant date | May 4, 1999 |
| Priority date | — |
| Expiry date | Apr 6, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An endurance testing system for an EEPROM mainly includes a microprocessor, an interface circuit, a high power pulse generator and a write/erase control and VT test circuit for automatically performing erase/write operations as many times as desired and displaying the variation of the difference between the threshold voltages respectively after the erase and the write operations so that the endurance of the EEPROM can be efficiently and correctly tested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.