Selecting phase assignments for candidate nodes in a logic network
US5903467A · kind A · utility
7Cited by
8References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 10, 1996 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Dec 10, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In designing a logic network a plurality of nodes are identified which define incompatible output phase assignments. Certain of the incompatible nodes are selected for assigning the output phases, so that NOT gates in the fan-out cone of such a selected node are moved to the network outputs. In a further aspect, the selecting is in response to the number of logic gates in the fan-in cones of the incompatible nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.