Electrically programmable memory cell
US5903494A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 19, 1997 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Nov 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5612
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A four state programmable memory cell includes a substrate of a first conductivity type having a channel region having a first side and a second side, a control gate located on a first insulating layer above the channel region, a drain region of a second conductivity type located on the substrate adjacent to the first side of the channel region, a source region of a second conductivity type located on the substrate adjacent to the second side of the channel region, a first insulated floating gate located on a second insulating layer above the drain region adjacent to the control gate, and a second insulated floating gate located on a third insulating layer above the source region adjacent to the control gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.