Low-supply-voltage nonvolatile memory device with voltage boosting
US5903498A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1997 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Jun 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The memory device has a plurality of local boost circuits, each connected to a sector of the memory array, and each having a control circuit, at least a respective boost capacitor, and a respective drive circuit. Each drive circuit is only enabled in read mode, on receiving an address-transition-detect signal and a sector enabling signal, for reading memory cells forming part of the respective sector. The boost voltage is only supplied to the final inverter of the row decoder. A clamping diode limits the boost voltage to prevent undesired direct biasing of the PMOS transistors of the final inverters connected to the nonaddressed word lines. And the overvoltage is therefore only supplied locally when and where necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.