Variable equilibrate voltage circuit for paired digit lines
US5903502A · kind A · utility
45Cited by
6References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 25, 1997 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Nov 25, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and circuit for rapidly equilibrating paired digit lines of a memory array of a dynamic random access memory device is described. The equilibrate circuit includes a bias-circuit coupled to sense amplifier circuitry for adjusting the equilibrate voltage during testing. A method is described for testing memory cell margin by adjusting the equilibrate voltage until an error is detected. The bias circuit is described as a pull-up transistor coupled to a common mode of a cross-coupled n-sense amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.