Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions
US5903505A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1997 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | May 19, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing refresh operations of a memory array wherein subthreshold leakage current may be set to near worst-case conditions. The memory array includes a first row of memory cells having a first memory cell configured to store a first memory value, and a second row of memory cells having a second memory cell configured to store a second memory value. The method comprises storing a logic high value to the first memory cell as the first memory value, followed by storing a logic low value to the second memory cell as the second memory value. The method further comprises repeatedly driving a write bit line coupled to both the first and second memory cells at a logic low level for a period of a time equal to a refresh interval corresponding to the first memory cell. Additionally, the method includes subsequently reading the first memory value from the first memory cell. Finally, the method includes indicating that the first memory cell is operating correctly if the first memory value is still equal to a logic high value, or indicating that the first memory value is malfunctioning if the first memory value is equal to a logic low value. Driving the write bit line low may be ac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.