Apparatus and method for automatically sequencing clocks in a data processing system when entering or leaving a low power state
US5903746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 4, 1996 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Nov 4, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock acquisition subsystem for a data processing system has an interlocked clock multiplexer 100 for acquiring a clock source which is provided as clock signal 102 to the data processing system. Multiplexer 100 has at least two inputs 104 and 106 for clock source signals. Each clock source signal can be connected to one or more clock sources 710 and 720. Control register 730 specifies which clock source is to be selected by the multiplexer. The multiplexer has an interlocked synchronizer on each clock signal input so that when the multiplexer is switched, output clock signal 102 transitions cleanly from a first clock source to a second clock source without glitches or runt pulses. While the data processing system is in a deep sleep low power mode, wakeup logic 750 can provide wakeup signal 751 to power down select logic 740 which automatically selects secondary clock 720 until primary clock 710 is operational.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.