Cache-based computer system employing memory control circuit and method for write allocation and data prefetch
US5903911A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1997 |
| Grant date | May 11, 1999 |
| Priority date | — |
| Expiry date | Jul 18, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0804
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache-based computer system is provided that attains the advantages of data prefetching while minimizing negative affects upon system bandwidth and overall system performance. When a microprocessor initiates a write cycle and a cache miss occurs, a master prefetch control circuit within a cache controller initiates a specialized bus transfer cycle referred to as a "write allocation and prefetch cycle". A slave prefetch control circuit responds to the initiation of the write allocation and prefetch cycle by latching the data from the microprocessor into a temporary storage element of a memory controller. The slave prefetch control circuit also initiates a burst read cycle simultaneously to access a corresponding block or line of prefetched data stored in system memory. The prefetched data is sequentially provided to the system bus and into the cache memory. Once the entire data block is read from system memory and transferred into the cache memory, the write data stored within the temporary storage element is written into the system memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.