Multiple 3-dimensional semiconductor device processing method and apparatus
US5904502A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 4, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Sep 4, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/09701
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making a multiple 3-dimensional semiconductor device substrate includes the steps of providing a plurality of devices each device including a semiconductor die and having a reference face requiring a subsequent face processing. The reference face of each of the plurality of devices is positioned upon a planar reference surface. The planar reference surface corresponds to a release layer having vacuum apertures disposed therein. The plurality of devices can be precisely aligned in a prescribed manner upon the release layer, wherein application of a vacuum source to the vacuum apertures holds the plurality of aligned devices at their respective reference faces upon the release layer. Molding compound is dispensed into gaps occurring between adjacent side faces of the plurality of devices other than the reference faces. Lastly, the molding compound is cured. A multiple 3-dimensional semiconductor device substrate is disclosed also.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.