Thomas G. Ference
45Patents
17h-index
47Co-inventors
81Inventor score
Filing activity: Apr 16, 1992 → May 6, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5977640A | Highly integrated chip-on-chip packaging | Electricity | 397 | Expired |
| US5935763A | Self-aligned pattern over a reflective layer | Physics | 203 | Expired |
| US5244143A | Apparatus and method for injection molding solder and applications thereof | Electricity | 186 | Expired |
| US5926029A | Ultra fine probe contacts | Physics | 114 | Expired |
| US6265771A | Dual chip with heat sink | Electricity | 113 | Expired |
| US5972765A | Use of deuterated materials in semiconductor processing | Electricity | 93 | Expired |
| US6294406A | Highly integrated chip-on-chip packaging | Electricity | 80 | Expired |
| US6271102A | Method and system for dicing wafers, and semiconductor structures incorporating the products thereof | Emerging Cross-Sectional Technologies | 63 | Expired |
| US6231333A | Apparatus and method for vacuum injection molding | Emerging Cross-Sectional Technologies | 59 | Expired |
| US6225699A | Chip-on-chip interconnections of varied characteristics | Electricity | 51 | Expired |
| US6611050B1 | Chip edge interconnect apparatus and method | Electricity | 48 | Expired |
| US6444490B1 | Micro-flex technology in semiconductor packages | Electricity | 42 | Expired |
| US5903045A | Self-aligned connector for stacked chip module | Electricity | 33 | Expired |
| US6221775A | Combined chemical mechanical polishing and reactive ion etching process | Electricity | 28 | Expired |
| US6368881B1 | Wafer thickness control during backside grind | Electricity | 19 | Expired |
| US6534389B1 | Dual level contacts and method for forming | Electricity | 18 | Expired |
| US6426241B1 | Method for forming three-dimensional circuitization and circuits formed | Electricity | 18 | Expired |
| US6887126B2 | Wafer thickness control during backside grind | Electricity | 17 | Expired |
| US6521977B1 | Deuterium reservoirs and ingress paths | Electricity | 16 | Expired |
| US6517944B1 | Multi-layer passivation barrier for a superconducting element | Electricity | 15 | Expired |
| US5904502A | Multiple 3-dimensional semiconductor device processing method and apparatus | Electricity | 14 | Expired |
| US6858941B2 | Multi-chip stack and method of fabrication utilizing self-aligning electrical contact array | Electricity | 14 | Expired |
| US6300687A | Micro-flex technology in semiconductor packages | Electricity | 12 | Expired |
| US6030855A | Self-aligned connector for stacked chip module | Electricity | 12 | Expired |
| US5793103A | Insulated cube with exposed wire lead | Electricity | 11 | Expired |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.