Method for fabricating a thin film transistor with the source, drain and channel in a groove in a divided gate
US5904515A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Nov 6, 2016 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/674
Abstract
A structure and fabrication method for a thin film transistor suitable for a SRAM memory cell. The thin film transistor structure includes a gate electrode formed to have a groove, a gate insulation film formed on the gate electrode, a semiconductor layer formed in the groove of the gate electrode, and impurity regions formed on opposite sides of the semiconductor layer. The method for fabricating the thin film transistor includes forming a gate electrode and a gate insulation film successively on an insulating substrate so as to have a groove, forming a semiconductor layer on the gate insulation film at a part of the groove, and forming source/drain impurity regions by selective injection of impurity ions into opposite sides of the semiconductor layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.