Fabrication process of semiconductor device
US5904558A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 13, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Feb 13, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31053
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is formed with an interlayer insulation layer having its high flatness. A metal wiring is formed on a silicon substrate via a silicon oxide layer. A multi-layer silicon oxide layer that is to be the interlayer insulation film is formed over the insulation layer and the metal wiring. The multi-layer silicon layer consists of an upper most first silicon oxide layer, a lower most third silicon oxide layer and an intermediate second silicon oxide layer. The second silicon oxide layer has higher polishing rate than the first and third silicon oxide layer. By performing chemical mechanical polishing for the multilayer silicon oxide layer, a step formed by the presence of the metal layer can be satisfactorily eliminated fox planarizing the surface of the interlayer insulation film.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.