Method of forming a MOS transistor having gate insulators of different thicknesses

US5905283A · kind A · utility

Assignee

• NEC CORPORATION · JP

Inventor

• Naoki Kasai · Tokyo, JP

Key dates

• Filing date: Apr 29, 1997
• Grant date: May 18, 1999
• Expiry date: Apr 29, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83

Abstract

The semiconductor device includes (A) a first MOS transistor including (a) a main surface at a part of which recesses are formed, an inner surface of the recesses defining a crystal plane being able to be thermally oxidized at higher speed than the main surface, and (b) an insulator formed on the inner surface of the recesses, the inner surface of the recesses working as a channel region and the insulator working as a gate insulator in the first MOS transistor, and (B) a second MOS transistor in which the main surface works as a channel region and an insulator formed on the main surface works as a gate insulator, the gate insulator of the first MOS transistor having a greater thickness than that of the gate insulator of the second MOS transistor. Thus, above the thinner gate insulator is formed the second MOS transistor, while above the thicker gate insulator is formed the first MOS transistor having a higher breakdown voltage than that of the second MOS transistor. Thus, the number of steps for forming insulators having different thicknesses can be reduced relative to prior methods. In addition, a resist layer is not directly deposited on a gate insulator unlike prior methods, a g…