CMOS SONET/ATM receiver suitable for use with pseudo ECL and TTL signaling environments
US5905386A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 27, 1998 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Feb 27, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A pulse receiver, comprising a pair of complementary symmetry metal oxide silicon (CMOS) common gate amplifiers connected between a 5 volt supply (ECL) voltage rail and an ECL ground (AGND), for receiving a pair of pulse input signals IN and INB and for providing a pair of first pulse signals, CMOS apparatus for distorting the first pulse signals, to create second pulse signals from the converter having a duty cycle having a longer low logic level interval than high logic level interval, a CMOS latch for receiving and latching the second output signals from the common gate amplifiers at logic levels compatible with circuits formed of CMOS elements, a CMOS double to single ended converter connected between a VDD voltage rail and VSS ground, for receiving the latched output signals, apparatus for providing an output signal referenced to VDD and ground from the converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.