Ferroelectric memory with feedback
US5905671A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Dec 22, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell includes a ferroelectric capacitor and a transistor connected between one side of the capacitor and a bit line. A drive circuit includes an operational amplifier having an output, an inverting input, and a non-inverting input. A plate line is connected between the other side of the capacitor and the output. The non-inverting input is connected to a data-in line through a first resistor and to the bit line through a second resistor. The inverting input is connected to a constant voltage source through a third resistor, and to the plate line through a fourth resistor. A first buffer amplifier is connected between the bit line and the second resistor, and a second buffer amplifier is connected between the plate line and the fourth resistor Voltage is connected to the other one of the operational amplifier inputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.