Dynamic memory
US5905685A · kind A · utility
Assignees
Inventors
Key dates
| Filing date | Oct 15, 1997 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Oct 15, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a dynamic RAM having a memory cell array in which a dynamic memory cell is arranged at an intersection between a word line and one of a pair of bit lines, a select level signal corresponding to a supply voltage and an unselect level signal corresponding to a negative potential lower than circuit ground potential are supplied to the word line. A signal of a memory cell read to the pair of bit lines by a sense amplifier that operates on the circuit ground potential and an internal voltage formed by dropping the supply voltage by an amount equivalent to the threshold voltage of the address select MOSFET is amplified. The dynamic RAM has an oscillator that receives the supply voltage and circuit ground potential and a circuit that receives an oscillation pulse generated by the oscillator to generate the negative potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.