Apparatus and method for storing interrupt source information in an interrupt controller based upon interrupt priority
US5905898A · kind A · utility
31Cited by
18References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Feb 23, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/90
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable interrupt controller is provided for use in computer systems including one or more CPUs. The programmable interrupt controller includes an interrupt request interface, a storage device, and at least one processor interface having an interrupt nesting buffer. An interrupt request identification code is assigned to each interrupt request and stored in the nesting buffer. The interrupt request identification codes used to reference the interrupt requests are stored in order of their priority. Each nesting buffer need have only a number of entries equal to the number of priority levels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.