System for implementing peripheral device bus mastering in a computer using a list processor for asserting and receiving control signals external to the DMA controller
US5905912A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 1996 |
| Grant date | May 18, 1999 |
| Priority date | — |
| Expiry date | Apr 8, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a system and method for implementing peripheral device bus mastering via a general purpose list processor. The system is comprised of four main elements: a bus controller, a DMA controller, a list processor, and a device controller. The system operates under two modes of operation. The two modes arise from the two distinct modules: the DMA controller and the list processor. The first mode of operation is a single buffer transfer mode which is directly compatible with a distributed DMA model. Under this mode, distributed DMA registers within the DMA controller are programmed to transfer a single contiguous buffer of data. The second mode of operation is a multiple buffer transfer mode which uses linked lists of buffer transfer descriptors to program the distributed DMA registers within the DMA controller and initiates transfers independent of software.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.