Gate coupled SCR for ESD protection circuits
US5907462A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1994 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | Sep 7, 2014 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D8/80
Abstract
A protection device comprising a gate-coupled silicon-controlled rectifier (SCR) (100), SCR (100) comprises an anode (105) formed in n-well (104) and connected to a pad (128) and a cathode (111) connected to ground. A gate-coupled NMOS transistor (120) has a gate (116) connected through a resistive element (118) to ground. A n+ region (112) forms both the cathode (111) and a source of the NMOS transistor (120). N-well (104) forms the drain. Stress voltage is coupled from pad (128) to gate electrode (116) causing NMOS transistor (120) to conduct. This, in turn, triggers SCR (100) which dissipates the stress current at the pad (128). The coupled voltage at gate electrode (116) dissipates within a designed time constant through resistive element (118).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.