MOSFET-based power supply clamps for electrostatic discharge protection of integrated circuits

US5907464A · kind A · utility

Assignee

• Intel Corporation · US

Inventors

• Timothy J. Maloney · Mountain Falls, US
• Travis Eiles · Beaverton, US

Key dates

• Filing date: Mar 24, 1997
• Grant date: May 25, 1999
• Expiry date: Mar 24, 2017

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/811

Abstract

Electrostatic discharge protection circuits adapted for use in low voltage CMOS processes have at least one PFET in the primary charge conduction path, and timer circuits configured to enable the primary conduction path during ESD events and to disable the primary conduction path during steady state conditions. In a further aspect of the present invention, bias circuits for maintaining steady state gate voltages below the dielectric breakdown level are included. In a still further aspect of the present invention a bridge circuit couples a first power supply node to a second power supply node, where the second power supply node is coupled to an ESD protection circuit.