Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance
US5907776A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 1997 |
| Grant date | May 25, 1999 |
| Priority date | — |
| Expiry date | Jul 11, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/393
Abstract
A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second conductivity type formed in the body region. A portion of the body region adjacent to the source region is compensated by ion implanting a material of the second conductivity type in the portion of the body region such that the impurity concentration of the body region at the portion is reduced. As a consequence, with reduced impurity charge in the body region adjacent to the source, the threshold voltage of the MOSFET device is lowered but at no comprise in punch-through tolerance because the reduction in charge is remote from the origin of the depletion layer which is located at the boundary between the body region and the epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.